1. Field of the Invention
The present invention relates to a method for measuring an effective channel length of a metal-oxide-semiconductor field effect transistor (MOSFET), and more particularly, to a method for measuring the effective channel length of the MOSFET and by using three compensation factors to accuratelydetermine positions of a drain and a source of the MOSFET.
2. Description of the Prior Art
Measuring the value of an effective channel length (Leffective) has always been one of the most important issues in the semiconductor industry to infer the characteristics of the MOSFET correctly. Furthermore, the effective channel length of the MOSFET is also one of the most important references for computer aided designing (CAD).
Please refer to FIG. 1 of a cross-sectional diagram of a metal-oxide-semiconductor field effect transistor (MOSFET) 10. The transistor 10 at least comprises a gate 12, a source 14, a drain 16 and a silicon substrate 18. Wherein an effective channel length of the transistor 10 is defined as the length of a channel 22 between the source 14 and the drain 16. The value of a threshold voltage VT of the transistor 10 is depended on the kind of the transistor 10, i.e., NMOS and PMOS etc. As the silicon substrate 18 and the source 14 are both grounded and a voltage greater than the threshold voltage VT of the transistor 10 is applied to the gate 12 of the transistor 10, the channel 22 is formed between the source 14 and the drain 16. In this case, a 0 volts voltage is applied to the source 14. Moreover, if and only if the voltage applied to the gate 12 is less than the threshold voltage VT of the transistor 10, the channel 22 vanishes, and the transistor 10 is in a cutoff mode and becomes non-conductive.
Normally, the method for measuring the effective channel length Leffective according to prior art regards the carrier mobility in the channel 22 as a constant for a group of devices with various channel lengths, or further simplified the carrier mobility in the channel 22 as a gate-bias-independent constant based on the assumption that the potential of the gate 12 is with a fixed value. However, this is not consistent with the reality that the Inversion carrier mobility Is determined by gate overdrive VGT, which is equal to the difference between the voltage of the gate VGS and the threshold voltage of the transistor VT, i.e.,VGT=VGSxe2x88x92VT Some techniques are thus proposed to obtain the effective channel length of the transistor more accurately by using the fixed gate overdrive VGT instead of the fixed gate bias. However, the bias dependence of the drain-and-source series resistance is not taken into account. In the conventional I-V (current-voltage) approach, a channel length loss xcex94 L and a series resistance RDS are needed to be extracted simultaneously and the RDS is assumed bias-independent so as to derive xcex94 L from the linear I-V equation. Unfortunately, the RDS is not bias-independent in fact, so that the accuracy of the xcex94 L obtained is flawed.
Please refer to FIG. 2 of the cross-sectional diagram of the MOSFET 10 shown in the FIG. 1 with a corresponding photomask 20. The photomask 20 is used for forming the gate 12 of the transistor 10 by lithography and etching processes during the manufacturing of the transistor 10. Wherein both the source 14 and the drain 16 are formed by performing ion implantation processes. During the lithography and etching processes, a polysilicon gate lithography bias Lbias is formed between the photomask 20 and the gate 12 so that a length of the photomask Lmask is not equal to a length of the gate Lgate. For simplicity of description, the length of the photomask 20 is assumed to be greater than the length of the gate 12 in FIG. 2. However, the length of the photomask Lmask is occasionally less than the length of the gate Lgate during different manufacturing processes. Alternatively, a metallurgical channel 23, the length of the metallurgical channel 23 being defined as the distance between the source 14 and the drain 16,exists in the transistor 10. Normally the effective channel length Leffective is greater than the length of the metallurgical channel 23.
The method for measuring the effective channel length of the transistor 10 according to the prior art is by way of measuring the voltage and the current between the source 14 and the drain 16. FIG.2 represents a current-voltage (I-V) approach method for measuring the effective channel length. By using the flowing equation below, the effective channel equivalent resistance Rchannel of the transistor 10 is obtained:                               R          channel                =                                            L              effective                                                      μ                eff                            ⁢                              C                ox                            ⁢                              W                ⁡                                  (                                                            V                      gate                                        -                                          V                      t                                                        )                                                              =                                    V              ds                                      I              ds                                                          (        1        )            
wherein xcexcaff is the effective mobility of the inversion carries;
Cox is the gate oxide capacitance per unit area;
W is the width of the transistor 10:
Vgate is the voltage applied to the gate 12;
Vt is the threshold voltage of the transistor 10;
Vds is the voltage between the source 14 and the drain 16; and
Ids is the current flows from the source 14 to the drain 16.
After the effective channel length Leffective is measured, the effective channel equivalent resistance Rchannel is capable of be calculated according to the equation (1), and the one-dimension model of the transistor 10 can be established thereafter. However, the method is merely capable of measuring the effective channel length Leffective of the transistor 10 and cannot be applied to measure the polysilicon gate lithography bias Lbias, and the overlap length 2Loverlap of the gate 12 and the source/drain 14/16. Consequently, the correct junction position of the source/drain 14/16 is not capable of being determined.
It is therefore a primary objective of the present invention to provide a method for measuring an effective channel length, a polysilicon gate lithography bias Lbias, and an overlap length of a gate and a source/drain 2Loverlap.
According to the claimed invention, a metal-oxide-semiconductor field effect transistor (MOSFET) has a silicon substrate, a gate, a drain, and a source. As the silicon substrate and the source are both grounded and a voltage greater than a threshold voltage of the transistor is applied to the gate of the transistor, a channel is formed between the drain and the source, and the transistor is operated in either an inversion mode or an accumulation mode. The method of measuring an effective channel length of the transistor comprising:
a. measuring a first unit length gate capacitance as the transistor is in the inversion mode, measuring a second unit length gate capacitance as the gate is grounded, and calculating a first compensation factor according to both the first unit length gate capacitance and the second unit length gate capacitance, wherein the first compensation factor is equal to a ratio of the first unit length gate capacitance to the second unit length gate capacitance;
b. measuring a first unit length overlap capacitance between the gate and the source/drain as the transistor is in the accumulation mode, measuring a second unit length overlap capacitance between the gate and the source/drain as the gate is grounded, and calculating a second compensation factor according to the first unit length overlap capacitance and the second unit length overlap capacitance, wherein the second compensation factor is equal to a ratio of the first unit length overlap capacitance to the second unit length overlap capacitance;
c. calculating a third compensation factor, the third compensation factor being equal to a ratio of the second compensation factor to the first compensation factor; and
d. calculating the effective channel length and an overlap length of the gate and the source/drain according to the first, second and third compensation factors.
It is an advantage of the present invention that not only the effective channel length is capable of be measured, but also the correct position of the source and the drain is capable of be determined.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.